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ADuC7060
I 2 C Address 1, I2CADR1, Register
I 2 C Master Clock Control, I2CDIV, Register
Name:
Address:
Default value:
Access:
Function:
I2CADR1
0xFFFF091C
0x00
Read and write
This 8-bit MMR is used in 10-bit addressing
mode only. This register contains the least
significant byte of the address.
Name:
Address:
Default value:
Access:
Function:
I2CDIV
0xFFFF0924
0x1F1F
Read and write
This MMR controls the frequency of the I 2 C
clock generated by the master on to the SCL
pin. For further details, see the Serial Clock
Generation section.
Table 99. I2CADR1 MMR in 10-Bit Address Mode
Bit Name Description
7:0 I2CLADR These bits contain ADDR[7:0] in 10-bit
addressing mode.
Table 100. I2CDIV MMR
Bit Name Description
15:8 DIVH These bits control the duration of the high
period of SCL.
7:0
DIVL
These bits control the duration of the low period
of SCL.
I 2 C Slave Registers
I 2 C Slave Control, I2CSCON, Register
Name:
Address:
Default value:
Access:
Function:
I2CSCON
0xFFFF0928
0x0000
Read and write
This 16-bit MMR configures the I 2 C peripheral
in slave mode.
Rev. 0 | Page 86 of 100
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